1. Technical Field of the Invention
This invention relates generally to integrated circuits and more particularly to testing of such integrated circuits.
2. Description of Related Art
As is known, speed, efficiency, and accuracy of testing integrated circuits is a critical component in the commercial success of an integrated circuit. For instance, if the integrated circuit test process does not accurately test the integrated circuits, then a significant number of field failures may occur, which would rapidly deteriorate its customer base. Further, if an accurate testing process is time consuming, the cost of such testing may render the integrated circuit commercially unviable. Still further, many integrated circuits are tested using automated test equipment (ATE), which may be a dedicated piece of equipment to test one type of integrated circuit or configurable to test multiple integrated circuits. As is known, the cost of automated test equipment increases substantially as the degree of configurability increases, which directly impacts the commercial viability of the corresponding integrated circuits.
A further issue with automated test equipment is the ever-increasing speed at which integrated circuits are transmitting, receiving and/or processing data. Thus, but for the most sophisticated and hence most expensive automated test equipment, such high-speed integrated circuits are tested on a pass/fail basis. For example, a field programmable gate array (FPGA) integrated circuit that includes a plurality of multi-gigabit transceivers, which can be configured to support multiple data transmission rates for a number of standards, is tested on a pass/fail basis at the most stringent of the data transmission rates for the most stringent standard requirements. Such testing is done in a loop-back configuration (e.g., the output of one multi-gigabit transceiver is tied to the input of another) using customized test equipment since no commercial tester is available. Such testing is done one multi-gigabit transceiver at a time, which adds to the duration of the overall test.
While such testing of an FPGA with multi-gigabit transceivers provides a pass/fail response, which indicates whether the FPGA integrated circuit can be sold, it provides no information regarding the reason for the failure, does not optimize yield, and is relatively slow due to the serial testing of the transceivers.
Therefore, a need exists for a method and apparatus for testing a system-on-a-chip that includes high-speed interfaces that improves yield, provides information regarding the reason for a failure, and is time efficient.